Advantech MIC-3358 User Manual download pdf (Page 64)

MIC-3358 User’s Manual 56

This field lets you insert a timing delay between the CAS and RAS strobe

signals, used when DRAM is written to, read from, or refreshed. Fast

gives faster performance; and Slow gives more stable performance. This

field applies only when synchronous DRAM is installed in the system.

The settings are: 2 and 3.

DRAM RAS# Precharge

If an insufficient number of cycles is allowed for the RAS to accumulate

its charge before DRAM refresh, the refresh may be incomplete and the

DRAM may fail to retain data. Fast gives faster performance; and Slow

gives more stable performance. This field applies only when synchronous

DRAM is installed in the system. The settings are: 2 and 3.

DRAM Data Integrity Mode

The settings are ECC (Default) and non-ECC.

Memory Frequency For

User can select 3 options: DDR200, DDR266, Auto (Default)

System BIOS Cacheable

Selecting Enabled allows caching of the system BIOS ROM at F0000h-

FFFFFh, resulting in better system performance. However, if any pro-

gram writes to this memory area, a system error may result. The settings

are: Enabled (Default) and Disabled.

Video BIOS Cacheable

Select Enabled allows caching of the video BIOS, resulting in better sys-

tem performance. However, if any program writes to this memory area, a

system error may result. The settings are: Enabled and Disabled

(Default).

Memory Hole At 15M-16M

You can reserve this area of system memory for ISA adapter ROM. When

this area is reserved, it cannot be cached. The user information of periph-

erals that need to use this area of system memory usually discusses their

memory requirements. The settings are: Enabled and Disabled (Default).

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Advantech MIC-3358 User Manual Page 64