Advantech MIC-3358 User Manual Page 65

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57 Chapter 4
Delayed Transaction
The chipset has an embedded 32-bit posted write buffer to support delay
transactions cycles. Select Enabled to support compliance with PCI spec-
ification version 2.1. The settings are: Enabled (Default) and Disabled.
4.1.5 Integrated Peripherals
Figure 4.5: Integrated Peripherals setup screen
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