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PCI-1730/1733/1734 User Manual 44

IDInF Interrupt flag bits (n = 0, 1, 16, 17)

This bit is a flag indicating the status of an interrupt. User can read this bit to get the

status of the interrupt

0 No interrupt

1 Interrupt occurred

IDInEN Interrupt enable control bits (n = 0, 1, 16, 17)

Read this bit to Enable/Disable the interrupt.

0 Disable

1 Enable

IDInRF Interrupt triggering control bits (n = 0, 1, 16, 17)

The interrupt can be triggered by a rising edge or falling edge of the interrupt signal,

as determined by the value in this bit.

0 Rising edge trigger

1 Falling edge trigger

C.9 Interrupt Control Register — BASE+8H/CH/10H

The PCI-1730 Interrupt Control Register controls the status of four interrupt signal

sources (IDI0, IDI1, DI0, DI1). The user can clear the interrupt by writing its corre-

sponding value to the Interrupt Control Register, as shown in below table.

Table C-10 Register for Interrupt Control

IDI/DInCLR Interrupt clear control bits (n = 0 ~ 1)

This bit must first be cleared to service the next interrupt.

0 Don’t care

1 Clear the interrupt

IDI/DInEN Interrupt enable control bits (n = 0 ~ 1)

Read this bit to Enable/Disable the interrupt.

0 Disable

1 Enable

IDI/DInRF Interrupt triggering control bits (n = 0 ~ 1)

The interrupt can be triggered by a rising edge or falling edge of the interrupt signal,

as determined by the value in this bit.

0 Rising edge trigger

1 Falling edge trigger

Write Interrupt Control Register

Bit #76543210

BASE + 8H DI1EN DI0EN IDI1EN IDI0EN

BASE + CH DI1RF DI0RF IDI1RF IDI0RF

BASE + 10H DI1CLR DI0CLR IDI1CLR IDI0CLR

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Advantech PCI-1730 User Manual Page 52