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45 PCI-1730/1733/1734 User Manual

Appendix C Register Structure & Format

The PCI-1733 Interrupt Control Register controls the status of four interrupt signal

sources (IDI0, IDI1, IDI16, DI17). The user can clear the interrupt by writing its corre-

sponding value to the Interrupt Control Register, as shown in below table.

Table C-11 Register for Interrupt Control

IDInCLR Interrupt clear control bits (n = 0, 1, 16, 17)

This bit must first be cleared to service the next interrupt.

0 Don’t care

1 Clear the interrupt

IDInEN Interrupt enable control bits (n =0, 1, 16, 17)

Read this bit to Enable/Disable the interrupt.

0 Disable

1 Enable

IDInRF Interrupt triggering control bits (n = 0, 1, 16, 17)

The interrupt can be triggered by a rising edge or falling edge of the interrupt signal,

as determined by the value in this bit.

0 Rising edge trigger

1 Falling edge trigger

Write Interrupt Control Register

Bit #76543210

BASE + 8H IDI17EN IDI16EN IDI1EN IDI0EN

BASE + CH IDI17RF IDI16RF IDI1RF IDI0RF

BASE + 10H

IDI17CLR IDI16CLR

IDI1CLR IDI0CLR

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Advantech PCI-1730 User Manual Page 53